Computer systems following conventional architectures include a central processing unit (CPU) and a main memory array which is used to store the applications and operating systems control programs which are executed by the CPU. A bus structure enables the CPU and main memory array to receive and send data to peripheral equipment such as input/output devices and auxiliary data storage and retrieval devices such as disk drives.
In one early era in the development of digital computers, main memory was comprised of an array of memory cores which were small electromagnetic toroidal cores manifesting hysteresis, i.e. a magnetic on-state and a magnetic off-state. The hand-wired core arrays were subsequently replaced by solid state semiconductor memory arrays. One type of array was known as static random access memory or SRAM, while another type of array was known as dynamic random access memory or DRAM. DRAMs typically required less power and provided superior data store and retrieval characteristics than were achieved with SRAMS. However, DRAMs, being dynamic in nature, required periodic refreshing operations to maintain the data.
DRAM technology has progressed to the point where single DRAM chips may provide as much as a megabit or four megabits, or more, of storage. For example, an array of eight one megabit chips provides a megabyte of data storage capacity while an array of 16 one megabit chips provides a megaword of data storage capacity. Larger capacity chips provide even greater storage capacities. In order to assure integrity of each bit position within a particular address location, several approaches have been followed. The simplest approach is a single additional parity bit position which checks the parity (odd or even) of the particular byte or word to be stored at the address and indicates an error if, as actually stored, the parity is different than anticipated.
Another approach is to provide an error correction scheme which requires as many as six extra bit positions for a 16 bit word. One example of such approach is provided by the Nagano et al. U.S. Pat. No. 4,394,763. This patent describes a method for detecting two-bit errors with an error correction code (ECC) scheme and then swapping a spare bit storage cell in place of a suspected defective cell and rerunning the bus memory transfer cycle. If only a single error remains, the ECC corrects this error and the process continues. In other words, the Nagano et al. approach was to provide dynamic bit swapping within an ECC scheme in order to replace bad bit cells with substitute good bit cells during operation of the memory array. The evident drawback of the Nagano et al. approach is that the ECC scheme requires considerable overhead in order to provide a six bit error correction code value for each sixteen bit word.
Another technique suggested by the prior art in Beausoleil U.S. Pat. No. 3,644,902 is to provide a mechanism for physically reconfiguring the boards comprising a memory array, so that an arrangement of boards in which a data word has a two bit error is changed to a new arrangement wherein a single bit error remains. Then, conventional ECC techniques may be used to correct for the single bit error.
DRAM chips are typically specified as having certain electrical characteristics. For computer service, characteristics such as power consumption, access times (speed), refresh rate, and freedom from nonfunctional storage locations are considered to be critical. Unfortunately, the manufacturing process is not yet sufficiently reliable in the megabit capacity ranges to provide full yields of chips that meet or exceed specifications relating to these four characteristics. However, a significant number of chips are produced which meet a slightly relaxed or less stringent set of specifications.
Since these chips cannot be reliably used within computer main memory, they are available at significantly lower cost than chips which meet the more stringent specifications for use within main memory of a digital computer. Other applications having relaxed specifications have been proposed and found for these chips, mostly within digital audio voice recording systems wherein single bit or several bit non-functionality will not perceptibly degrade reconstituted audio information. One application is for storing digital messages within telephone answering machines. Thus, these chips have come to be known within the semiconductor industry as "AUDIO DRAM".
The problem of storage media defects has been encountered and solved within disk drives. Disk drives store data in concentric data tracks formed at the surface of one or more rotating disks carrying a magnetic coating. Each concentric data track or cylinder location of a fixed disk drive is typically formatted into a number of data sectors. Each sector typically includes a sector header and storage space to store a 512 byte block of data, followed by an error correction code space for ECC data. While many conventional ECC techniques used in disk drives can detect two hard (i.e., repeating) bit errors, and correct one or two bit errors within a predetermined bit span, ECC techniques break down when more errors are present within the span.
In order to compensate for multiple data bit defects within a sector or block, the data track or cylinder location may be provided with a spare sector, so that during a data format operation, the spare sector may be pressed into service to provide storage for a sector determined to have a media defect. In one known approach, the defective sector is skipped over during the format operation and its storage capacity made up by pressing the spare sector into service. In another approach, a seek or head select is made to the spare sector in lieu of the defective sector in accordance with a defect map to which the disk drive controller has direct access. These techniques are collectively referred to in the disk drive art as "sector sparing".
A hitherto unsolved need has arisen for the practical utilization of Audio DRAM within computing systems in order to realize a low cost, high storage capacity solid state memory array.